IP Cores

PCIe 2.0 Controller IP Core，compliance to PCI Express 2.0 Specification，provides high bandwidth and high reliability solution for serial data comunitation. The core can be used in many applications which may have different perforance/complexity/resource requirents, through the provided configurable parameters.
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Part Code: ip_pcie2_ctrl

PCIe 3.0 Controller IP Core，compliance to PCI Express 3.0 Specification，provides high bandwidth and high reliability solution for serial data comunitation. The core can be used in many applications which may have different perforance/complexity/resource requirents, through the provided configurable parameters.
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Part Code: ip_pcie3_ctrl

PCIe AXI Memory Mapped Bridge IP，transforms the PCIe user data bus from AXI Stream to AXI memory mapped Bus. It implements two Vendor Specified Extanded Capalibity (VSEC), which may linked to PCIe Configuration Space. VSEC can be accessed by user through simple AXI Lite Bus, that provides a simple way for user to control PCIe Controller. VSEC also supports flexible address translation between PCIe address space and user's memory space.
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产品编码: ip_pcie_mmb

The Core implements NVMe protocol (Host Function) using pure logic, and connects to the user system through standant AMBA bus, easing integration. User operates IP core using the provided Software driver (c code), and manipulates NVMe SSD through the provided private Queue. The Core supports two address mapping manner for data in the user system: Serial and Strip.
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Part Code: ip_nvme_host_ctrl

A hardware accelerator of the queue management for NVMe commands and completions. Provides the NVMe register interface for both host communication and controller management.
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Part Code: ip_nvme_target_ctrl

Optimized for NAND Flash 512B/1KB code block. Customizable maximum ECC level. High performance or low complexity implementation available. Ideal ECC code for the traditional SLC/MLC NAND Flash.
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Part Code: ip_nand_bch_512_1k

2KB code data block of high code rate(0.9014 ). Irregular QC LDPC with optimized degree distribution and large girth (8). Error floor is not more than 10^-15. Ideal ECC code for the novel high density TLC/3D NAND Flash.
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Part Code: ip_nand_ldpc_2k_90r

Boyuan NAND Flash Controller (NFC) with LDPC Codec IP Core provides a Register Transfer Level (RTL) solution for the SLC/MLC/eMLC NAND Flash memories. The integrated higher performance BCH core guarantees the high reliability with the steady high read and write throughput from the early to the End-Of-Life (EOF) of NAND Flash memories.
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Part Code: ip_nfc_onfi4_bch

Boyuan NAND Flash Controller (NFC) with LDPC Codec IP Core provides a Register Transfer Level (RTL) solution for the novel NAND Flash memories. The Core guarantees the industry reliably for NAND Flash applications and provides standard interface that easies the integration.
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Part Code: ip_nfc_onfi4_ldpc

BCH(392,248) codec corrects up to 16 bit random error within 392B code block. BCH(1920,1744) codec corrects up to 16 bit random error within 1920B code block. BCH(1920,1044) code corrects up to 89 bit random error within 1920B code block. Optimized for more than 1Gbps application.
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Part Code: ip_hinoc20_bch_codec