Boyuan Technology Co. Ltd
BCH NAND Codec IP Core
The BCH IP core for NAND Flash is to correct random errors occured in data frame. The BCH encoder generates parity bits and the BCH decoder finds & corrects error bits using three sub-modules: Error Detect Coder (EDC), Key Equation Solver (KES) and Chien Search Machine (CSM). These sub-modules are scheduled in a pipeline manner, which mean the BCH decoder can decode three data frames concurrently with each frame in each decoding stage. The KES module is optimized to get equivalent latency with other sub-modules. The CSM is implemented area efficiently using BOYUAN's proprietary technologies.
Impletation
Applications
The core can be utilized in the controller of a variety of NAND Flash including:
- SLC/MLC NAND Flash
- Few serials of TLC NAND Flash
Parity Length
| 512B Data Block | ||
|---|---|---|
| ECC Level | 8bit | 24bit |
| Parity Length | 13B | 39B |
| 1KB Data Block | |||||||
|---|---|---|---|---|---|---|---|
| ECC Level | 8bit | 24bit | 32bit | 40bit | 48bit | 72bit | 96bit |
| Parity Length | 14B | 42B | 56B | 70B | 84B | 1001bit | 1337bit |
Request more ECC Levels: tech@bjbytech.com
Port Map
Encoder Port Map:
Decoder Port Map:
Block Diagram
Encoder Block Diagram:
Decoder Block Diagram:
Features
- Synchronoused design
- Supported data block: 512B, 1KB, etc.
- Support multiple ECC levels
- Parameterized input data width
- Parameterized output data width
- Full pipelined decoder
- Report decoding results
Standard Interface Timing
- valid/ready data transfer protocol
- data source set/clear valid
- data destination set/clear ready
Downloads (PDF)
Related Products
Sales E-mail: sale@bjbytech.com
Technical consult E-mail: tech@bjbytech.com
Cell Phone: +8613601005061
Support
The core as delivered is warranted against defects for three months from purchase. Free remote technical support is provided for twelve months, includes consultation via phone and E-mail. The maximum time for processing a request for technical support is three business days.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements.
Deliverables
The core is available in RTL source code (Verilog) and FPGA (Netlist) forms, and includes everything required for successful implementation:
- RTL source code or post-synthesis EDIF Netlist (FPGAs)
- Wrapper for pin compatible replacement
- Testbench (self-checking)
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications