Boyuan Technology Co. Ltd
-
IP core reduces
Time-to-MarketInstant access to cutting-edge technologies in few weeks of integration instead of several months of in-house Research & Design.
Boyuan provides a series of fully validated IP cores that can be flexibly licensed to chip designers/FPGA system developers in a variety of ways to speed up their product launch time.
-
Customization is More Suitability.
Modular designed IP Core, easy to customize feature & interface. Application decides the trade-off between performance and power.
Most Boyuan's IP cores support customization of functionality, performance and interface timing. Futhermore a free evaluation FPGA netlist can be requested by the customer before formal license.
What We Do?
Specializes in digital IP cores for semiconductors, primarily in NAND Flash storage controller and interface area as well as other ECC cores in communication area. We provides a full NAND Flash IP Core solution.
How We Do?
The features, performance, resource usage and interface can be customizable to fit the customer's application using our our professional skills. A free evaluation netlist can be requested before formal license.
Our Support!
One year on-line consultation and technical support through phone, e-mail and WeChat. Help our customer to integrate the IP core(s) to their ASIC chips or FPAG systems successfully. Customer's success is our first priority.
IP Cores
- PCIe Controller
- NVMe Controller
- NAND Flash ECC
- NAND Flash Controller
- HINOC 2.0 FEC
License Benefits:
- Netlist for FPGA or Full Source Code (RTL Verilog)
- Royalty-free and No Quantitative Restrictions
- Free Remote Technical Support for 12 Months
- Worldwide
Update News & Events
12th January 2024 BOYUAN releases PCIe 3.0 Controller IP v3.10
PCIe 3.0 Controller IP v3.10 release notes：
Compliance PCIe 3.0
Lane Width Configurable：x1，x2，x4，x8。
Suport Root port，End Point。
Maximum Payload Support: 128B，256B，512B，1024B。
User I/F：Full duplex，4 independent AXI Stream bus
Private Replay Manner to share TX Buffer and Replay Buffer
Dual clock design, Link CRC generating and checking in user clock domain, easy for implementation.
Support AXI Memory Mapped Bridge. (Optional)
Integration Service using Xilinx PHY (Ultra & Ultra+, Optional).
Integration Service using Xilinx PHY (7, Optional): Support 8BG/s using 3rd-part 128b/130b PCS Core.
30th December 2021 BOYUAN updates NVMe Host Controller IP-AMBA v21.10
NVMe Host IP-AMBA v21.10 update notes：
Update TLP Packet/Un-Packet Engine to improve I/O performance.
Native RAID0 feature, easy to construct RAID controller.
Support BOYUAN PCIe Controller.
Support Core direct usage mode: Register user command I/F, FIFO/RAM style data I/F.
Support RAID0/1/5 (Optional).
20th December 2021 BOYUAN releases PCIe 2.0 Controller IP v21.00
PCIe 2.0 Controller IP v21.00 release notes：
Compliance PCIe 2.0
Lane Width Configurable：x1，x2，x4。
Suport Root port，End Point。
Maximum Payload Support: 128B，256B，512B。
User I/F：Full duplex，4 independent AXI Stream bus
Private Replay Manner to share TX Buffer and Replay Buffer
Dual clock design, Link CRC generating and checking in user clock domain, easy for implementation.
Support Data Link Layer direct usage, user implement their own Transaction Layer.
Integration Service using Xilinx PHY (7, Ultra & Ultra+, Optional).
20th September 2018 New Website is Online
BOYUAN's new website is now on line. The customers can get more information about our IP Core products.
15th February 2018 Boyuan release new LDPC IP Core for TLC/3D NAND Flash.
BOYUAN finds a new LDPC algorithm to solve new TLC/3D NAND Flash reliability issue. The algorithm has 18176bit code length and 0.9014 code rate. The code has girth 8 and sub-matrix is 256. We have carried out a large number of FPGA experiments.The NMS decoding algorithm paramters are backward optimized by our proprietary technologies using the experiment data. The result is satisfactory (error flow is not more than 10-15). More NEWs